TTTC: DATA 2012 Call for Participation - Discount Registration Deadline Oct. 5th!

Advance Discount Registration Deadline October 5, 2012!

CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

It just never stops. Every year silicon wafer process technology continues to shrink, more transistors and functions are included into designs, and customers continue to demand even lower dppm. Meanwhile our bosses and managers are always looking at test as an area to reduce product cost, and they expect us to be able to reduce our test costs while also meeting these newer and tougher test challenges and quality goals. So how do we do it?

“How to get more out of test” has led to new methods to learn about defects and IC behavior through the use of innovative analysis techniques. Now questions about how these techniques should be executed and controlled in production, the types and sizes of databases, and even the format and storage of test data itself are becoming critical. Complex problems, such as the control and documentation of dynamic test changes during Adaptive Test, ensuring high quality levels without test escapes, and the practical and realistic limitations of new ideas for board/system testing are all hot industry topics. Closing the knowledge gap about these issues, the processes, the new test techniques, new database requirements, and how defect models and failure data can be used to adapt test flows are the goals of the DATA workshop.

Key Dates

top

Advance Discount Workshop Registration Deadline: October 5, 2012
Advance Discount Hotel Reservation Deadline: October 22, 2012
Advance Park Ticket Sales Deadline: November 11, 2012

The Venue

top

Hotel and venue information can be found on the Hotel/Travel webpage.

Workshop Registration

top

To register for the workshop only or workshop and ITC please use the registration website.

Advance Program

top

Thursday -- Friday

November 8, 2012 (Thursday)

4:00 PM - 5:00 PM	Session 1 - Opening & Keynote
4:00 - 4:15	Opening Remarks Jeff Roehr (Texas Instruments), General Chair Arani Sinha (Intel), Program Chair
4:15 - 5:00	Keynote Dan Glotter (CEO, Optimal Test)

5:00 PM - 7:00 PM	Session 2 - Adapting to Adaptive Test
5:00 - 5:30	Adaptive Alternate Analog Test Haralampos-G. Stratigopoulos, Salvador Mir (TIMA Laboratory)
5:30 - 6:00	Spatial Correlation Modeling For Probe Test Cost Reduction (Invited talk) Yiorgos Makris (UT Dallas)
6:00 - 6:30	Seven Precautions for Statistical Parametric Test Analysis Jeff Tikkanen, Nik Sumikawa, Li-C Wang (UC Santa Barbara), LeRoy Winemberg, Magdy S. Abadir (Freescale)
6:30 - 7:00	Chip Level DFT hooks for System Test and Reconfigurability (Invited Talk) Sreejit Chakravarty ( LSI Logic)

7:00 PM - 9:00 PM Workshop Welcome Reception

November 9, 2012 (Friday)

8:00 AM - 9:00 AM	Session 3 - Embedded Tutorial
	Noise and Variability Challenges in Delay Testing Adit Singh (Auburn University)

9:00 AM - 10:30 AM	Session 4 - A Good Die, or an Outlier: New Ways to Tell
9:00 - 9:30	Mathematical Framework for Selecting Tests for Outlier Detection H.C.M. Bossers, J.L. Hurink, G.J.M. Smit (University of Twente)
9:30 - 10:00	Improving Test Quality Using Data Mining – A Case Study Harry H. Chen, Roger Hsu, J.J. Shyr, PaulYoung Yang, ChingCheng Wang (Mediatek)
10:00 - 10:30	Outlier Detection – A Comprehensive Guide to Business & Technical Implementation Keith Arnold (Salland Engineering), Peter M. O'Neill (Avago Technologies), Don W. Hartman (Test CIM Consulting)

10:30 AM - 10:50 AM Coffee Break

10:50 AM - 11:50 AM	Session 5 - The Power Hour
10:50 - 11:10	Current-Based Dynamic Technique for Accurately Predicting Power-Supply Noise and Path Delay Sushmita Kadiyala Rao, Ryan Robucci, Chintan Patel (University of Maryland, Baltimore)
11:10 - 11:30	On the impact of multiple clock domains and intermodulation products on test C. Thibeault, J. Larche (Ecole de technologie superieure, Montreal)
11:30 - 11:50	Test time reduction using Adaptive DFT Methodology for SOCs Darshan Kobla, Sankaran Menon (Intel)

11:50 AM - 1:00 PM Lunch

1:00 PM - 2:20 PM	Session 6 - What do I do with my data?
1:00 - 1:20	An Extensible Architecture for Transitioning Distributed Test Data to Cloud-Based Analytics Devin Morris, Oscar Rodriguez, Joe Barnhart, Mark Roos (Roos Instruments)
1:20 - 1:40	Post-Silicon Defect Level Estimation from Test Data Kanad Chakraborty (Lattice Semiconductor), Vishwani D. Agrawal (Auburn University)
1:40 - 2:00	Decision Tree Induction from Semiconductor Test Data William Tambellini (Galaxy Semiconductor)
2:00 - 2:20	Test Process Production Triage Steve Ledford (Advantest)

2:20 PM - 2:30 PM Coffee Break

2:30 PM - 3:00 PM	Session 7 - ITRS Roadmap Update
	Data Latency issues in ITRS roadmap for Adaptive Test Jeff Roehr, Texas Instruments

3:00 PM - 4:15 PM	Panel Discussion - ITRS Adaptive Test Data Flow: Tomorrowland or Fantasyland? Organizers: Wes Smith (Galaxy Semi), Jennifer Dworak (SMU)

More Information

top

Technical Program Submissions
Arani Sinha
Intel, USA.
E-mail: Arani.Sinha@INTEL.com

General Information
Jeffrey Roehr
Texas Instruments, USA.
E-mail: JLRoehr@TI.com

Committees

top

GENERAL CHAIR
Jeffrey Roehr, Texas Instruments

PROGRAM CHAIR
Arani Sinha, Intel

VICE-PROGRAM CHAIR
Jennifer Dworak, SMU

PANEL CHAIR
Wesley Smith, Galaxy

FINANCE CHAIR
Sankaran Menon, Intel

PUBLICITY CHAIR
Kanad Chakraborty, Lattice Semiconductor

PUBLICATIONS CHAIR
Chintan Patel, UMBC

STEERING COMMITTEE
Sankaran Menon, Intel
Adit Singh, Auburn Univ.
M. Tehranipoor, U Connecticut
Hank Walker, Texas A&M
Hans Manhaeve, Q-Star Test
Jim Plusquellic, U. New Mexico

PROGRAM COMMITTEE
Rob Aitken, ARM
Nemat Bidokhti, Cisco
Sreejit Chakravarty, LSI
John Carulli, TI
Jennifer Dworak, SMU
Patrick Girard, LIRMM, France
Ajay Khoche, Consultant
Mike Laisne, Qualcomm
Amit Nahar, TI
Suriyaprakash Natarajan, Intel
Jay Orbon, Consultant
John Potter, Asset-Intertech
Rajesh Raina, Freescale
Claude Thibeault, ETS, Canada
Li C. Wang, UCSB
Xiaoqing Wen, KIT, Japan
Qiang Xu, CUHK, Hong Kong

For more information, visit us on the web at: http://DATA.tttc-events.org/

The IEEE International Workshop on Defect & Adaptive Test Analysis (DATA 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).